module fifo_syn_ram(clk,
                    wr_en,
                    wr_addr,
                    wr_addr_r,
                    rd_en,
                    rd_addr,
                    data_in,
                    data_out
                    );
  input clk,wr_en,rd_en;
  input [5:0]wr_addr;
  input [5:0]rd_addr;
  input [7:0]data_in;
  //input rst;
  input [5:0]wr_addr_r;
  output [7:0]data_out;
  
  reg [7:0]data_out;
  reg [7:0]ram[63:0];
  reg [63:0] i,tmp;
  wire clk,wr_en,rd_en;
  wire [7:0]data_in;
  always@(posedge clk or wr_en)
    begin
      if(wr_en)
        begin
          if(wr_addr_r<wr_addr)
          begin
          ram[wr_addr_r]=data_in;

          end
          else
          ram[wr_addr]=data_in;
        end
      
    end
  always@(posedge clk or rd_en)
    begin
      if(rd_en)
        begin
            data_out=ram[rd_addr];
            for(i=1;i<wr_addr;i=i+1)
            begin
               tmp=ram[i];
               ram[i-1]=tmp;
            end
            ram[wr_addr-1]=64'hx;
   //         wr_addr=wr_addr-1;
        end
      
    end
/*
always @(negedge rst)
begin
    for(i=0;i<64;i=i+1)
    ram[i]=8'bX;
end
*/
endmodule  
  
